2013 Kyoto Prize Laureates

Advanced Technology

Electronics

Robert Heath Dennard

/  Electronics Engineer

1932 - 2024

IBM Fellow, Thomas J. Watson Research Center, IBM Corporation

Commemorative Lectures

Reflections on Creativity in My Microelectronics Career

2013

11 /11 Mon

Place:Kyoto International Conference Center

Workshop

Integrated Circuits: 50 Years of Their Evolution and Future Prospects

2013

11 /12 Tue

10:00 - 17:00

Place:Kyoto International Conference Center

Achievement Digest

Invention of Dynamic Random Access Memory and Proposal of Guidelines for FET Miniaturization

Dr. Robert Heath Dennard invented the basic structure of Dynamic Random Access Memory (DRAM), which is now extensively utilized as one of integrated circuit (IC) memory systems. His innovation has immensely increased the capacity of digital information storage, leading to dramatic progress in information and telecommunications technology. Dr. Dennard and his colleagues also proposed guidelines, called “scaling theory”, to miniaturize field-effect transistors, which play key roles in most ICs, including DRAM, thereby promoting the amazing advance in IC technology.

Citation

Dr. Robert Heath Dennard invented the basic structure of the Dynamic Random Access Memory (DRAM) which is now utilized extensively as one of integrated circuit (IC) memory systems. This innovation has immensely increased the capacity of digital information storage, leading to dramatic progress in information and telecommunications technology. Dr. Dennard and his colleagues also proposed design guidelines for miniaturizing MOS (metal oxide semiconductor) field-effect transistors (FETs), which play key roles in most ICs, including DRAM, thereby promoting the amazing advance in IC technology.

Dr. Dennard began working on memory ICs for computers in the 1960s and invented the basic DRAM structure in 1967. Its fundamental memory unit, or cell, consists of one FET (hereinafter, “transistor”) and one capacitor; each cell stores one bit of data as “1” or “0” by controlling the presence or absence of an electric charge on the capacitor. Cells are arranged on a chip in a matrix form and connected to grid-like wire lines to create a DRAM. The system is called random access memory because it permits any memory cell to be accessed in random order by the selection of a specific horizontal “word” line and a vertical “bit” line, unlike the sequential access memory provided by tape storage.

To store digital information, one bit of data, “1” or “0”, is written in each cell by supplying or removing an electric charge on its capacitor through the transistor. Because the charge thus stored on each capacitor gradually drains away, it is necessary to refresh the capacitor periodically, leading to the name “dynamic” RAM, or DRAM. To read the binary data of a cell, the presence or absence of a stored charge on the capacitor is detected by precisely measuring a change in the electric potential of the bit line.

In 1970, 1k-bit DRAM chip using a three-transistor cell was commercially released, while Dr. Dennard’s one-transistor design made its market debut in 1973. Since then, all the DRAMs have been produced by incorporating the single-transistor structure.

In addition to his DRAM invention, Dr. Dennard and his coworkers studied how FET characteristics changed when they were scaled down, and proposed design guidelines (scaling theory) useful for FET miniaturization. This facilitated the integration of more FETs on a single chip, increasing DRAM storage capacity more than one million-fold, while permitting drastic improvement in the speed and performance of microprocessors and other ICs.

These achievements by Dr. Dennard brought about remarkable developments in integrated circuit technologies, which provided the essential foundation for tremendous progress in information and communications equipments.

For these reasons, the Inamori Foundation is pleased to present the 2013 Kyoto Prize in Advanced Technology to Dr. Robert Heath Dennard.

Profile

Biography
1932
Born in Texas, U.S.A.
1958
Ph.D. in Electrical Engineering, Carnegie Institute of Technology (now Carnegie Mellon University)
1958
Staff Engineer, IBM Research, IBM Corporation
1963
Research Staff Member, Thomas J. Watson Research Center, IBM Corporation
1973
Group Manager, Thomas J. Watson Research Center, IBM Corporation
1982
Manager of MOS Devices and Circuits, Silicon Technology Department, Thomas J. Watson Research Center, IBM Corporation
1979
IBM Fellow, Silicon Technology Department, Thomas J. Watson Research Center, IBM Corporation
Selected Awards and Honors
1988
National Medal of Technology and Innovation, U.S. Government
1997
Inducted into National Inventors Hall of Fame
2006
C&C Prize, NEC C&C Foundation
2007
Benjamin Franklin Medal in Electrical Engineering, The Franklin Institute
2009
Charles Stark Draper Prize, National Academy of Engineering
2009
IEEE Medal of Honor, IEEE (The Institute of Electrical and Electronics Engineers)
Members
National Academy of Engineering, IEEE, American Philosophical Society
Selected Publications
1968
Field-Effect Transistor Memory, U.S. Patent 3,387,286, June 4, 1968.
1974
Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions (with Gaensslen, F. H. et al.), IEEE Journal of Solid-State Circuits SC9: 256-268, 1974.
1975
Fabrication of a Miniature 8K-Bit Memory Chip Using Electron-Beam Exposure (Yu, H. N., Dennard, R. H. et al.), Journal of Vacuum Science and Technology 12: 1297-1300, 1975.
1984
Evolution of the MOSFET Dynamic RAM - A Personal View, IEEE Transactions on Electron Devices 31: 1549-1555, 1984.
1997
Scaling Challenges for DRAM and Microprocessors in the 21st Century, in Electrochemical Society Proceedings 97-3: 519-532, 1997.

Profile is at the time of the award.

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